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? semiconductor components industries, llc, 2005 november, 2005 ? rev. 1 1 publication order number: ncp5603/d ncp5603 high efficiency charge pump converter the ncp5603 is an integrated circuit dedicated to the medium power white led applications. the power conversion is achieved by means of a charge pump structure, using two external ceramic capacitors, making the system extremely tiny. the device supplies a constant voltage to the load from a low battery voltage source. it is particularly suited for the high efficiency led used in low cost, low power applications, with high extended battery life. features ? wide battery supply voltage range: 2.7 < v cc < 5.5 v ? automatic operating mode 1x, 1.5x and 2x improves efficiency ? dimmable output current ? up to 350 ma output pulsed current ? selectable output voltage ? high efficiency up to 90% ? supports 2.5 kv esd, human body model ? supports 200 v machine model esd ? low 40 ma short circuit current ? pb?free package is available applications ? high power led ? back light display ? high power flash http://onsemi.com dfn10 mn suffix case 485c 5603 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package marking diagram 5603 alyw 3 c2p v bat 2 c1p v out 8 gnd 9 10 c1n (top view) 1 fsel 4 vsel 5 7 c2n 6 en pin connections device package shipping ? ordering information NCP5603MNR2 qfn10, 3x3 3000/ tape & ree l NCP5603MNR2g qfn10, 3x3 (pb?free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 3000/ tape & ree l
ncp5603 http://onsemi.com 2 v bat c1p 3 2 9 c1 1 f/16 v c1n en/pwm 6 fsel 4 vsel 5 gnd 8 gnd v bat ncp5603 c2n c2p c2 7 10 v out d1 lwt67c r1 10 d2 lwt67c r2 d3 lwt67c r3 d4 lwt67c r4 figure 1. typical application u1 4.7 f/16 v c3 gnd 1 1 f/16 v gnd gnd c4 1 f/16 v vsel fsel pwm 10 10 10
ncp5603 http://onsemi.com 3 figure 2. block diagram logic and analog control 4 5 6 v bat thermal shutdown level shifter and mosfet drive power switches v bat + ? gnd v bat gnd bandgap gnd 1 v out v out 2 c1p 9 c1n 7 c2n 10 c2p 3 v bat v bat fsel vsel en 8 gnd
ncp5603 http://onsemi.com 4 pin function description pin symbol type description 1 v out output, pwr this pin supplies the regulated voltage to the external led. since high current transients are present in this pin, care must be observed to avoid voltage spikes in the system. good high frequency layout technique must be observed. 2 c1n power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c1p, pin 9. using low esr ceramic capacitor is recommended to optimize the charge pump efficiency. 3 v bat power this pin shall be connected to the power source, and must be decoupled to ground by a low esr capacitor (2.2 f/6.3 v ceramic or better (see note 1)). 4 fsel input, digital this pin is used to program the operating frequency: fsel = 0 fop = 262 khz fsel = 1 fop = 650 khz 5 vsel input, digital this pin setup the output voltage: vsel = 0 v out = 4.5 v vsel = 1 v out = 5.0 v 6 en/pwm input, digital this pin controls the activity of the ncp5603 chip: en/pwm = low the chip is deactivated, the load is disconnected en/pwm = high the chip is activated and the load is connected to the regulated output current. the ncp5603 can operate either in a continuous mode (en/pwm = high), or can be controlled by a pwm pulse applied to en/pwm to dim the output light. when en/pwm is low, the external load is disconnected from the converter, providing a very low standby current. the pull down built?in resistance makes sure the chip is deactivated even if the en/pwm pin is disconnected (see note 2). 7 c2n power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c2p, pin 10. using low esr ceramic capacitor is recommended to optimize the charge pump efficiency. 8 gnd ground this pin combines the signal ground and the power ground and must be connected to the system ground. using good quality ground plane is mandatory to avoid spikes on the logic signal lines. 9 c1p power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c1n, pin 2. using low esr ceramic capacitor is recommended to optimize the charge pump efficiency. 10 c2p power one side of the external charge pump capacitor is connected to this pin, associated with c2n, pin 7. using low esr ceramic capacitor is recommended to optimize the charge pump efficiency. 1. using ceramic 16 v working voltage capacitors is recommended to compensate the dc bias effect encountered with such type of capacitor s. 2. any external impedance connected to pin 6 shall be 10 k or higher.
ncp5603 http://onsemi.com 5 maximum ratings rating symbol value unit power supply voltage v bat 7.0 v power supply current i bat 800 ma digital input pins v in ?0.5 v < vbat < vbat +0.5 v < 6.0 v v digital input pins iin 5.0 ma output voltage v out 5.5 v esd capability (note 3) human body model machine model v esd 2.5 200 kv v qfn10, 3x3 package power dissipation @ tamb = +85 c thermal resistance, junction?to?air (r ja ) p ds r ja 580 68.5 mw c/w operating ambient temperature range t a ?40 to +85 c operating junction temperature range t j ?40 to +125 c maximum junction temperature t jmax +150 c storage temperature range t stg ?65 to +150 c latchup current maximum rating 100 ma per jedec standard, jesd78 moisture sensitivity level (msl) 1 per ipc/jedec standard, j?std?020a maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 3. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.5 kv per jedec standard: jesd22?a114 machine model (mm) 200 v per jedec standard: jesd22?a115. 4. the maximum package power dissipation limit must not be exceeded.
ncp5603 http://onsemi.com 6 electrical characteristics @ 2.85 v < vbat < 5.5 v (?40 c to +85 c ambient temperature, unless otherwise noted). characteristic pin symbol min typ max unit power supply 3 v bat 2.85 ? 5.5 v quiescent current @ v bat = 3.7 v, i out = 0 a @ pulsed clock fop = 262 khz @ pulsed clock fop = 650 khz @ continuous clock fop = 262 khz @ continuous clock fop = 650 khz 3 iqsc ? ? ? ? ? ? 1.0 2.1 0.8 1.2 ? ? ma shutdown current @ i out = 0 ma, en/pwm = l @ 2.85 < v bat < 4.2 v @ v bat = 5.5 v 3 i stdb ? ? ? ? 2.5 4.0 a output voltage regulation @ vsel = 1, 2.85 v < v bat < 4.5 v @ vsel = 0, 2.85 v < v bat < 4.5 v 3 v out 4.75 4.275 5.0 4.5 5.25 4.725 v continuous dc load current (note 7) cin = 1.0 f, c fly = 1.0 f, cout = 1.0 f @ vsel = 1, 3.2 v < v bat < 4.5 v @ vsel = 0, 3.2 v < v bat < 5.5 v @ vsel = 1, 2.85 v < v bat < 4.5 v @ vsel = 0, 2.85 v < v bat < 5.5 v 3 i out ? ? ? ? ? ? ? ? 160 200 80 120 ma pulsed output current cin = 10 f, c fly = 1.0 f, cout = 10 f, v bat = 3.6 v pwidth = 500 ms, ?40 c < t a < +65 c 3 i flh ? 350 ? ma output continuous short circuit current, v out = 0 v 3 isch ? 40 100 ma operating frequency (note 5) @ fsel = 0, 2.85 v < v bat < 4.5 v @ fsel = 1, 2.85 v < v bat < 4.5 v fop 210 500 262 650 320 1000 khz output voltage ripple (note 6) fop = 262 khz, i out = 60 ma (note 7) @ c out = 1.0 f @ c out = 4.7 f 3 v pp ? ? 150 25 ? 60 mv digital input high level 4, 5, 6 v ih 1.3 ? ? v digital input low level 4, 5, 6 v il ? ? 0.4 v output power efficiency @ v bat = 3.3 v, v out = 5.0 v, i out = 60 ma, fop = 262 khz @ v bat = 3.9 v, v out = 5.0 v, i out = 160 ma, fop = 650 khz p ? ? 75 84 ? ? % thermal shut down protection hysteresis t hsd ? ? 160 20 ? ? c 5. temperature range guaranteed by design, not production tested. 6. smaller footprint associated to lower working voltages (10 v or 6.3 v, size 0805 or 0602) can be used, but care must be observed to pre vent dc bias effect on the capacitance final value. see capacitor manufacturer data sheets. 7. ceramic x7r, esr < 100 m , smd type capacitors are mandatory to achieve the i out specifications. depending upon the pcb layout, it might be necessary to use two 2.2 f/6.3 v/ceramic capacitors in parallel, yielding an improved v out noise over the temperature range. on the other hand, care must be observed to take into account the dc bias impact on the capacitance value. see ceramic capacitor m anufacturer data sheets. 8. digital inputs undershoot < ? 0.30 v to ground, digital inputs overshoot < 0.30 v to v bat .
ncp5603 http://onsemi.com 7 typical characteristics 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 efficiency (%) v in (v) figure 3. operating modes transitions and output power efficiency @ v out = 4.5 v/262 khz figure 4. operating modes transitions and output power efficiency @ v out = 4.5 v/650 khz figure 5. operating modes transitions and output power efficiency @ v out = 5.0 v/650 khz figure 6. typical output voltage ripple figure 7. typical output voltage line regulation figure 8. output voltage startup from scratch i out = 120 ma 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5 .5 efficiency (%) v bat (v) i out = 120 ma 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 efficiency (%) v bat (v) 4.2 4.3 4.4 4.5 4.6 4.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v bat (v) ?40 c v out (v) 4.7 25 c 85 c ?40 c 25 c 85 c test conditions: v bat = 3.6 v, v out = 5 v, load = 4*lw87s, i led = 25ma i out = 160 ma i out = 200 ma
ncp5603 http://onsemi.com 8 typical characteristics test conditions: v bat = 3.6 v, v out = 5 v, load = 4*lw87s, i led = 25ma figure 9. typical pwm dimming v bat c1p 3 2 9 c1n en/pwm 6 fsel 4 vsel 5 gnd 8 gnd ncp5603 c2n c1p c2 1 f/16 v 7 10 v out 1 c2 1 f/6.3 v v cc r1 1 gnd gnd figure 10. typical high power flash circuit c1 10 f/10 v c4 10 f d1 osram: lww5sg golden dragon gnd pwr?flash gnd en fsel vsel
ncp5603 http://onsemi.com 9 0 100 200 300 400 500 2.5 3.0 3.5 4.0 4.5 v bat (v) figure 11. ncp5603 output current v out = 4.5 v fsel = 0 load = osram / lww5sg pwr switch = mgsf1n03 50 150 250 350 450 i out (ma) r = 2.2 r = 0 r = 1 table 1. ceramic preferred capacitors manufacturer type/series format value tdk c3216x5r1c475mt 1206 4.7 f / 16 v tdk c2012x5r1c225mt 0805 2.2 f / 16 v tdk c2012x5r1c105mt 0805 1.0 f / 16 v
ncp5603 http://onsemi.com 10 6 1 u2a nl27wz14 4 3 u2b nl27wz14 + + v bat c1p 3 2 9 c1n en/pwm 6 fsel 4 vsel 5 gnd 8 gnd vsel fsel ncp5603 c2n c1p c2 1 f/16 v 7 10 v out v cc d1 lw67c r6 c3 1.0 f/16 v gnd u1 1 gnd d2 lw67c r7 d3 lw67c r8 d4 lw67c r9 82 tp2 tp1 v out i sense 1 1 c1 1 f/16 v v cc r4 10 k gnd r5 10 k gnd s3 s2 vsel fsel c7 100 nf c4 4.7 f/16 v gnd r3 10 k p1 200 ka s4 gnd 4 mm j1 v cc 4 mm j2 gnd power gnd 2 34 pk1 2 x 1.5 v ? + 1 gnd q q c6 100 nf 2 1 4 5 3 6 7 rc c a b clr r2 100 k r1 c5 33 nf s1 v cc gnd q q 14 15 12 11 13 10 9 rc c a b clr cnt/pwm gnd gnd c8 100 nf gnd ground z3 r11 1.5 k gnd v cc r10 10 k v cc gnd d5 pwm u3a mc14538b u3a mc14538b u3b mc14538b figure 12. evaluation board schematic diagram adjust pwm 82 82 82
ncp5603 http://onsemi.com 11 figure 13. evaluation board: silk view (top view)
ncp5603 http://onsemi.com 12 package dimensions dfn10 mn suffix case 485c?01 issue a 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. ???? ???? ???? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.45 2.55 e 3.00 bsc e2 1.75 1.85 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters
ncp5603 http://onsemi.com 13 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp5603/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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